To fabricate microelectronic semiconductor devices such as an integrated circuit (IC), many different layers of metal interconnects and their surrounding insulation are deposited and patterned above the transistor layer on a silicon wafer. The insulation layers may be, for example, silicon dioxide, silicon oxynitride, fluorinated silicate glass (FSG), organosilicate glass (OSG, SiCOH), and the like. These insulation layers are deposited between the metal interconnect layers, i.e., interlevel dielectric (ILD) layers, and may act as electrical insulation therebetween.
The metal interconnect layers are interconnected by metallization through vias etched in the intervening insulation layers. Additionally, interconnects are provided separately within the dielectric (insulation) layers. To accomplish this, the stacked layers of metal and insulation undergo photolithographic processing to provide a pattern consistent with a predetermined IC design. By way of example, the top layer of the structure may be covered with a photo resist layer of photo-reactive polymeric material for patterning via a mask. A photolithographic process using either visible or ultraviolet light is then directed through the mask onto the photo resist layer to expose it in the mask pattern. An antireflective coating (ARC) layer may be provided at the top portion of the wafer substrate to minimize reflection of light back to the photo resist layer for more uniform processing. Regardless of the fabrication process, to maximize the integration of the device components in very large scale integration (VLSI), it is necessary to increase the density of the components.
Although silicon dioxide material has been used as an insulating material due to its thermal stability and mechanical strength, in recent years it has been found that better device performance may be achieved by using a lower dielectric constant material. By using a lower dielectric constant insulator material, a reduction in the capacitance of the structure can be achieved which, in turn, increases the device speed. However, use of organic low-k dielectric material such as, for example, SiCOH, tends to have lower mechanical strength than conventional dielectric materials such as, for example, silicon oxide.
By building a device having a low-k dielectric or a hybrid low-k dielectric stack, the large intra-level line-to-line component of wiring capacitive coupling is reduced, thus maximizing the positive benefit of the low-k material while improving the overall robustness and reliability of the finished structure. The hybrid oxide/low-k dielectric stack structure is much more robust than an “alllow-k” dielectric stack, but with a concomitant increase in wiring capacitance relative to the alllow-k stack. As insulator dielectric constants continue to be decreased, for example by adding porosity to the low-k material such as SiCOH, the overall dielectric mechanical strength continues to decrease as well.
Nonetheless, even with the lower dielectric constant materials including, for example, a hybrid oxide/low-k dielectric stack structure, there is still the possibility to improve even further the electrical propel iies of the device by lowering the effective K (Kerf) of a multilevel structure or a K of the dielectric material by forming voided channels (conventionally referred to as “air gaps”, though they may not contain air) within the dielectric material between the interconnects and vias. The channels are vacuum filled and have a dielectric constant of about 1.0, and represent a dielectric sub- structure between the metal interconnects in the IC. By using such channels, the Keff of a higher dielectric constant insulator may be lowered significantly without reducing its mechanical strength by nearly as much.
There may be additional reasons for creating other types of dielectric sub-structures between the metal interconnects. For example, porous ultralow-k insulator surfaces may need to be strengthened or repaired after chemical-mechanical polishing or plasma precleans prior to cap depositions, to improve their time dependent dielectric breakdown (TDDB) reliability. Similar to the air gap process, this might require sub-lithographic patterning to define regions where sub-structure processes are effective.
In known systems, sub-resolution lithography processes have been used to create such channels. This typically consists of new manufacturing processes and tool sets which add to the overall cost of the fabrication of the semiconductor device. Also, in sub-resolution lithography processes, it is necessary to etch wide troughs in empty spaces which, in turn, cannot be pinched off by ILD PECVD deposition. Additionally, although the channels create low line-line capacitance, there remains a high level-level capacitance for wide lines. This, of course, affects the overall electrical properties of the device. Also, air gaps can occur near the vias from a higher level which creates the risk of plating bath or metal fill at these areas. Lastly, in known processes, there is also the requirement of providing an isotropic etch which may etch underneath the interconnect thus leaving it unsupported or floating and, thus degrading the entire structural and electrical performance of the device.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.